AI Engines Programmable Logic (FPGA fabric) Embedded processing subsystem Memory architecture and data movement
Implement selected lens-free imaging algorithms on the Versal platform. Evaluate different acceleration approaches and partitioning strategies. Benchmark performance against CPU and/or GPU reference implementations. Identify architectural bottlenecks and optimization opportunities. Research Questions The thesis aims to answer questions such as: will lens-free imaging algorithms benefit most from Versal AI Core acceleration? What performance gains can be achieved compared to conventional CPU or GPU execution? How does power efficiency compare across implementation options? What are the limitations and challenges when deploying computational imaging pipelines on heterogeneous adaptive SoCs? Methodology The student will: Phase 1: Literature Review Review lens-free imaging concepts and applications. Investigate the Versal AI Core architecture and development tools. Phase 2: Algorithm Analysis Characterize computational complexity, memory bandwidth, and parallelization opportunities for the selected algorithms. Phase 3: Hardware Acceleration Implement selected kernels on the Versal platform. Explore multiple architecture mappings:
CPU-only FPGA acceleration AI Engine acceleration Hybrid implementations Phase 4: Benchmarking Measure:
Execution time Throughput Latency Resource utilization Power consumption Energy per reconstructed image Phase 5: Evaluation and Recommendations Compare implementation approaches. Identify best practices for future computational imaging systems. Provide design guidelines for deploying lens-free imaging on Versal-based platforms. Expected Results The thesis is expected to deliver: A comprehensive performance analysis of lens-free imaging workloads on Xilinx Versal AI Core. Optimized hardware-accelerated implementations of selected reconstruction algorithms. Quantitative benchmarking results against conventional computing platforms. Recommendations for future imaging system architectures leveraging adaptive computing technologies. Required Skills Preferred background: Digital design and FPGA development C/C++ programming Embedded systems Signal processing or image processing Basic knowledge of AI/ML acceleration is a plus Type of internship : Master internship Duration : 6 months Required educational background : Computer Science, Other, Electrotechnics/Electrical Engineering Supervising scientist(s) : For further information or for application, please contact Abelardo Gonzalez Diaz ( Abelardo.GonzalezDiaz@imec.be ) The reference code for this position is 2026-INT-317 . Mention this reference code in your application. Imec allowance will be provided for students studying at a non-Belgian university. Applications should include the following information: resume motivation current study Incomplete applications will not be considered
Bron: de eigen carrièresite van de werkgever. We linken naar de originele vacature.